---
description: >-
  During my journey of learning Assembly, i was taking some notes .. and now,
  I'm sharing it openly with you <3 ...
---

# Assemby + C - Part # 2

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### Background: Endianess

* Endianess comes from jonathan Swift's Gulliver's Travels. In which people go to war over the correct way to eat soft boiled eggs!
* Little Endian - 0x12345678 stored in RAM "little end first". The least significant byte (LSB) of a word or larger is stored in the lowest address. E.g 0x78, 0x56, 0x34, 0x12
* Big Endian - 0x12345678 stored in RAM "big end" first. The most significant byte (MSB) of a word or larger is stored in the lowest address. Eg: 0x12,0x34, 0x56, 0x78
  * Network traffic is sent Big Endian (do "man byteorder" to see POSIX network-to-host oredering functions)
  * Many RISC systems (PowerPC, SPARC, MIPS, Motorola 68k) started as Big Endian but can now be configured as either (Bi-Endian). ARM started out Littled Endian and now is Bi-Endian.
* Endianess applies to memory, not registers
* Endianess applies to bytes, not bits

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#### Endianess visualization

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#### How you'll probably usually see endianness expressed:

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If you start asking the debugging to display things, 2, 4, or 8 bytes at a time. it will typically take those chunks and display them each big endian order.

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#### Endianness example in GBD

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If you start asking the debugging to display things, 2, 4, or 8 bytes at a time. it will typically take those chunks and display them each big endian order.

### Computer Memory Hierarchy

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### x86-64 general purpose registers

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#### Architecture - Registers

* Registers are small memory storage areas built into the processor (still volatile memory)
* Intel has 16 "general purpose" registers + instruction pointer which points at the next instruction to execute
  * But 2 of the 16 are not that general
* On x86-32, registers are 32 bits wide
* On x86-64, registers are 64 bits wide

#### Intel Register Evolution

* 8-bit 8008

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* 16-bit 8086

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* 32 bit 80386

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* 64-bit AMD Opteron / Intel Pentuim 4&#x20;

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&#x20;Or the new naming format as the following:

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For more you can visit the following link: https://www.csie.ntu.edu.tw/\~cyy/courses/assembly/09fall/lectures/handouts/lec12\_x86arch\_4up.pdf

#### Intel recommended register conventions

There are Intel's suggestions to compiler developers (and assembly handcoders). Registers don't have to be used these ways, but if you see them being used like this, you'll know why. But I simplified some descriptions. I also coded as GREEN for the ones which we will actually see in the following parts (as opposed to future ones), and RED for not.

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https://learn.microsoft.com/en-us/cpp/build/x64-software-conventions?view=msvc-160





